uwb-rescue-locator
Lucas-Poulos
Components (31)
| Reference | Value | Description |
|---|---|---|
| Q1 | AO3401A | |
| U1 | MCP73871 | |
| U2 | MAX17048G+T10 | |
| U3 | ESP32-S3-WROOM-1 | Espressif ESP32-S3-WROOM-1 Wi-Fi/BLE MCU module, on-board PCB antenna variant (non-U). 41 pins, verified against datasheet v1.8 Table 3-1 -- see bay-station/libs/components.csv. |
| U4-U7 | DWM3000 | Qorvo/Decawave DWM3000 UWB transceiver module -- see shared/README.md and shared/symbols/uwb_rescue_locator_shared.kicad_sym for full verification notes. |
| U8 | TPS62A02PDDCR | 2.5-5.5V in, 2A synchronous buck, adjustable output, SOT-23-6. See lib_symbols description and regulation_notes.md for full verification. |
| BT1 | 3.7V Li-Ion (JST-PH pigtail) | |
| C1,C5 | 10uF | Unpolarized capacitor |
| C2,C3,C20 | 4.7uF | TPS62A02 VIN decoupling, 4.7uF X7R per datasheet Table 8-2 recommended component (Murata GRM21BR71A475KA73L, 0805) -- sized 0805 rather than 0603 given the DC-bias-derating concern already flagged for power_bms.kicad_sch's C1 (10uF/0603). |
| C4 | 0.1uF | |
| C6-C9,C11,C12,C14,C15,C17,C18 | 100nF | Unpolarized capacitor |
| C10,C13,C16,C19,C23 | 1uF | EN (U3 pin 3, reset) RC delay capacitor, 1uF to GND -- other half of the RC delay circuit alongside R22, per the real Espressif ESP32-S3 Hardware Design Guidelines Schematic Checklist ('R = 10 kOhm and C = 1 uF').,Unpolarized capacitor |
| C21 | 22uF | TPS62A02 +3V3_SYS output decoupling, 22uF X7R per datasheet Table 8-2 recommended component (Murata GRM21BZ71A226KE15L, 0805) and Table 8-3's recommended L=1uH/Cout=22uF combination for VOUT>=1.8V (the '++' proven-stable combination). |
| C22 | 120pF | Optional feedforward capacitor across R8 (FB divider top resistor), 120pF per datasheet's own Application Information note ('a feedforward capacitor reduces output ripple in PSM and improves load transient response; a 120pF capacitor is good for the 1.8V output typical application') -- included here since this rail also uses PSM, per the same design intent. |
| D1 | MBRA140T3G | |
| D2,D3 | ESD5B5.0ST1G | |
| J1 | CUI PJ-063AH | |
| J2 | USB4125-GF-A | |
| J3 | USB_C_Receptacle_USB2.0_14P | Dedicated data-capable USB-C receptacle for native-USB programming/debug (D+/D- to U3 pins 14/13 per connectivity.kicad_sch). Real KiCad-default part (Connector:USB_C_Receptacle_USB2.0_14P). Needed because the board's existing USB-C receptacle (J2, power_bms.kicad_sch) is Connector:USB_C_Receptacle_PowerOnly_6P and has no D+/D- pins at all -- see this sheet's note text for the full reasoning. A real data-capable USB-C connector footprint (e.g. GCT USB4105-xx-A 16P) is used as a placeholder footprint pick; verify/replace at BOM time same as this board's other generic connectors. |
| L1 | 1uH | Power inductor, 1uH, >=2A saturation current per TPS62A02 datasheet Table 8-3/Table 8-2 recommended component list -- e.g. Coilcraft XGL3520-102MEC (2A-rated) or Murata DFE252012F-1R0M (1A-rated, only if using the 1A TPS62A01 variant instead). No exact KiCad default footprint match found for XGL3520; pick exact footprint/PN at BOM time. |
| R1,R9,R25-R28 | 100k | TPS62A02 feedback divider, bottom resistor (FB to GND). R2 = 100k per datasheet's own worked example and its 'R2 must not be higher than 100k for acceptable noise sensitivity' guidance -- used at exactly the recommended ceiling value. |
| R2 | 2.00k | |
| R3 | 20.0k | |
| R4 | 330k | |
| R5 | 110k | |
| R6,R7,R23,R24 | 5.1k | J3 CC1 pulldown, 5.1k to GND -- standard USB-C UFP-device pulldown so any host/PD source enables VBUS at default 5V/current, matching the identical R6/R7 convention already used for J2 on power_bms.kicad_sch.,J3 CC2 pulldown, 5.1k to GND -- see R23. |
| R8 | 453k | TPS62A02 feedback divider, top resistor (VOUT to FB). R1 = R2 x (VOUT/VFB - 1) = 100k x (3.3V/0.6V - 1) = 450k per datasheet Eq.2 -- 453k is the nearest standard E96 1% value (100k x 4.53), giving VOUT = 0.6V x (1 + 453k/100k) = 3.318V. |
| R10-R22 | 10k | EN (U3 pin 3, reset) pull-up to +3V3_SYS, 10k -- half of the RC delay circuit. Per the real Espressif ESP32-S3 Hardware Design Guidelines (Schematic Checklist, docs.espressif.com/projects/esp-hardware-design-guidelines/en/latest/esp32s3/schematic-checklist.html): 'The recommended setting for the RC delay circuit is usually R = 10 kOhm and C = 1 uF.',GPIO0 (U3 pin 27) pull-up to +3V3_SYS, 10k. GPIO0=1 (SPI Boot / normal boot) per Espressif ESP32-S3-WROOM-1 Datasheet v1.8 Table 4-3 'Chip Boot Mode Control'; default strap state is already weak-pull-up (Table 4-1) but this makes it explicit per the datasheet's own recommendation ('It is recommended to place a pull-up resistor at the GPIO0 pin').,GPIO3 (U3 pin 15) pull-down to GND, 10k. Espressif ESP32-S3-WROOM-1 Datasheet v1.8 Section 4.4 'JTAG Signal Source Control': 'The strapping pin GPIO3 ... does not have any internal pull resistors and the strapping value must be controlled by the external circuit that cannot be in a high impedance state.' Default eFuse JTAG-source config (Table 4-5, all-zero) ignores GPIO3 for source selection, so pull direction is not functionally critical yet, but an external pull is required by the datasheet's own text regardless.,GPIO45 (U3 pin 26) pull-down to GND, 10k. Selects VDD3P3_RTC-derived 3.3V SPI-flash voltage per Espressif ESP32-S3-WROOM-1 Datasheet v1.8 Table 4-4 'VDD_SPI Voltage Control' (GPIO45=0 -> 3.3V via R_SPI, matching this module's standard 3.3V-flash variant, not the -N16R16VA 1.8V variant) -- matches GPIO45's own default weak-pull-down (Table 4-1), made explicit.,GPIO46 (U3 pin 16) pull-down to GND, 10k. Espressif ESP32-S3-WROOM-1 Datasheet v1.8 Table 4-1 default is weak-pull-down; the combination GPIO46=1 with GPIO0=0 is explicitly called out by Espressif as invalid/may trigger unexpected behavior, so GPIO46 is pulled down to guarantee a valid boot-mode strap combination alongside R18/SW1.,GPIO5 (GPIO5/EXTTXE/SPIPOL, U4 pin 10) SPI-mode-strap pull-down, 10k to GND -- explicitly defines SPI mode 0 (SPIPOL=0/SPIPHA=0) at power-up, per the real Qorvo DWM3000 Data Sheet Rev B 'Sample GPIOs 5&6 to set SPI mode' power-up step (Figures 1/2) and Section 6.3 (see this sheet's note text). Reinforces the DWM3000's own internal 10k-30k pull-down default (Section 6.3) with an explicit external resistor.,GPIO5 (GPIO5/EXTTXE/SPIPOL, U5 pin 10) SPI-mode-strap pull-down, 10k to GND -- explicitly defines SPI mode 0 (SPIPOL=0/SPIPHA=0) at power-up, per the real Qorvo DWM3000 Data Sheet Rev B 'Sample GPIOs 5&6 to set SPI mode' power-up step (Figures 1/2) and Section 6.3 (see this sheet's note text). Reinforces the DWM3000's own internal 10k-30k pull-down default (Section 6.3) with an explicit external resistor.,GPIO5 (GPIO5/EXTTXE/SPIPOL, U6 pin 10) SPI-mode-strap pull-down, 10k to GND -- explicitly defines SPI mode 0 (SPIPOL=0/SPIPHA=0) at power-up, per the real Qorvo DWM3000 Data Sheet Rev B 'Sample GPIOs 5&6 to set SPI mode' power-up step (Figures 1/2) and Section 6.3 (see this sheet's note text). Reinforces the DWM3000's own internal 10k-30k pull-down default (Section 6.3) with an explicit external resistor.,GPIO5 (GPIO5/EXTTXE/SPIPOL, U7 pin 10) SPI-mode-strap pull-down, 10k to GND -- explicitly defines SPI mode 0 (SPIPOL=0/SPIPHA=0) at power-up, per the real Qorvo DWM3000 Data Sheet Rev B 'Sample GPIOs 5&6 to set SPI mode' power-up step (Figures 1/2) and Section 6.3 (see this sheet's note text). Reinforces the DWM3000's own internal 10k-30k pull-down default (Section 6.3) with an explicit external resistor.,GPIO6 (GPIO6/EXTRXE/SPIPHA, U4 pin 9) SPI-mode-strap pull-down, 10k to GND -- explicitly defines SPI mode 0 (SPIPOL=0/SPIPHA=0) at power-up, per the real Qorvo DWM3000 Data Sheet Rev B 'Sample GPIOs 5&6 to set SPI mode' power-up step (Figures 1/2) and Section 6.3 (see this sheet's note text). Reinforces the DWM3000's own internal 10k-30k pull-down default (Section 6.3) with an explicit external resistor.,GPIO6 (GPIO6/EXTRXE/SPIPHA, U5 pin 9) SPI-mode-strap pull-down, 10k to GND -- explicitly defines SPI mode 0 (SPIPOL=0/SPIPHA=0) at power-up, per the real Qorvo DWM3000 Data Sheet Rev B 'Sample GPIOs 5&6 to set SPI mode' power-up step (Figures 1/2) and Section 6.3 (see this sheet's note text). Reinforces the DWM3000's own internal 10k-30k pull-down default (Section 6.3) with an explicit external resistor.,GPIO6 (GPIO6/EXTRXE/SPIPHA, U6 pin 9) SPI-mode-strap pull-down, 10k to GND -- explicitly defines SPI mode 0 (SPIPOL=0/SPIPHA=0) at power-up, per the real Qorvo DWM3000 Data Sheet Rev B 'Sample GPIOs 5&6 to set SPI mode' power-up step (Figures 1/2) and Section 6.3 (see this sheet's note text). Reinforces the DWM3000's own internal 10k-30k pull-down default (Section 6.3) with an explicit external resistor.,GPIO6 (GPIO6/EXTRXE/SPIPHA, U7 pin 9) SPI-mode-strap pull-down, 10k to GND -- explicitly defines SPI mode 0 (SPIPOL=0/SPIPHA=0) at power-up, per the real Qorvo DWM3000 Data Sheet Rev B 'Sample GPIOs 5&6 to set SPI mode' power-up step (Figures 1/2) and Section 6.3 (see this sheet's note text). Reinforces the DWM3000's own internal 10k-30k pull-down default (Section 6.3) with an explicit external resistor. |
| SW1 | BOOT | BOOT button: momentary switch from GPIO0 (U3 pin 27) to GND. Pulling GPIO0 low at reset enters Joint Download Boot mode (Table 4-3, ESP32-S3-WROOM-1 Datasheet v1.8) for flashing over the native USB port (J3). Standard practice on ESP32-S3 dev boards. Generic 2-pin tactile switch (e.g. Panasonic EVQ-PUJ or C&K PTS645-series) -- pick exact footprint/PN at BOM time, same convention as this board's other generic connectors. |
| SW2 | RESET | RESET button: momentary switch from EN (U3 pin 3) to GND. Standard manual-reset practice on ESP32-S3 dev/debug boards, alongside the R22/C23 RC delay. Generic 2-pin tactile switch (e.g. Panasonic EVQ-PUJ or C&K PTS645-series) -- pick exact footprint/PN at BOM time. |
| TH1 | 10k NTC |