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hprd
UT Austin Fall 2025-Spring 2026 Senior Design Project for developing a Zilog Z80 CPU drop-in replacement using an FPGA.
| Reference | Value | Description |
|---|---|---|
| IC1-IC10 | NXB0104PW-Q100J | Translation - Voltage Levels 3 STATE DUAL SUPPLY TRANS |
| U1 | 501MLF | |
| U2 | CD74AC109M96 | |
| C1-C21,C23 | 100nF | Unpolarized capacitor |
| J1,J4 | Conn_02x24_Odd_Even | Generic connector, double row, 02x24, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/) |
| J2,J3 | Conn_01x20_Pin | Generic connector, single row, 01x20, script generated |
| R1-R10 | 100k | Resistor, small symbol |