dmg-schematics
msinger
Reverse engineered schematics of the Game Boy's DMG-CPU B chip
Components (179)
| Reference | Value | Description |
|---|---|---|
| U?,U?,U? | NOR7_IF1_OD | Open-drain NOR gate with seven inputs and enable input. |
| U?,U?,U? | NOR5_IF1_OD | Open-drain NOR gate with five inputs and enable input. |
| U? | NOR12_IF1_OD | Open-drain NOR gate with twelve inputs and enable input. |
| U?,U?,U?,U? | NOR6_IF1_OD | Open-drain NOR gate with six inputs and enable input. |
| U? | OR4 | OR gate with four inputs. |
| U? | NOR11_IF1_OD | Open-drain NOR gate with eleven inputs and enable input. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND3_OD | Open-drain NAND gate with three inputs. |
| U?,U? | AND8 | AND gate with eight inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U? | OR2 | OR gate with two inputs. |
| U?,U?,U?,U? | NAND8_OD | Open-drain NAND gate with eight inputs. |
| U?,U?,U?,U?,U?,U?,U? | NAND10_OD | Open-drain NAND gate with ten inputs. |
| U?,U?,U? | NAND13_OD | Open-drain NAND gate with thirteen inputs. |
| U?,U?,U? | AND12 | AND gate with twelve inputs. |
| U?,U?,U?,U? | AND9 | AND gate with nine inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND4_OD | Open-drain NAND gate with four inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND5_OD | Open-drain NAND gate with five inputs. |
| U?,U?,U?,U?,U?,U?,U? | NAND11_OD | Open-drain NAND gate with eleven inputs. |
| U? | NOR20_IF1_OD | Open-drain NOR gate with twenty inputs and enable input. |
| U?,U?,U?,U?,U?,U?,U? | AND6 | AND gate with six inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND2_OD | Open-drain NAND gate with two inputs. |
| U?,U? | AND10 | AND gate with ten inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND7_OD | Open-drain NAND gate with seven inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | OR3 | OR gate with three inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND9_OD | Open-drain NAND gate with nine inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND6_OD | Open-drain NAND gate with six inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | AND5 | AND gate with five inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,ZYOC? | AND3 | AND gate with three inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,ZIUL? | AND2 | AND gate with two inputs. |
| U?,U? | NAND14_OD | Open-drain NAND gate with fourteen inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NOR4_IF1_OD | Open-drain NOR gate with four inputs and enable input. |
| U? | NOR75_IF1_OD | Open-drain NOR gate with seventy-five inputs and enable input. |
| U? | NOR37_IF1_OD | Open-drain NOR gate with thirty-seven inputs and enable input. |
| U? | NOR13_IF1_OD | Open-drain NOR gate with thirteen inputs and enable input. |
| U? | NOR40_IF1_OD | Open-drain NOR gate with fourty inputs and enable input. |
| U? | NOR24_IF1_OD | Open-drain NOR gate with twenty-four inputs and enable input. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NOR3_IF1_OD | Open-drain NOR gate with three inputs and enable input. |
| U? | NOR29_IF1_OD | Open-drain NOR gate with twenty-nine inputs and enable input. |
| U? | NOR48_IF1_OD | Open-drain NOR gate with fourty-eight inputs and enable input. |
| U? | NOR44_IF1_OD | Open-drain NOR gate with fourty-four inputs and enable input. |
| U?,U?,U? | NAND12_OD | Open-drain NAND gate with twelve inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | AND4 | AND gate with four inputs. |
| U? | AND7 | AND gate with seven inputs. |
| U? | NOT_OD | Open-drain inverter. |
| U? | NOR31_IF1_OD | Open-drain NOR gate with thirty-one inputs and enable input. |
| U? | NOR17_IF1_OD | Open-drain NOR gate with seventeen inputs and enable input. |
| U? | NOR46_IF1_OD | Open-drain NOR gate with fourty-six inputs and enable input. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NOR2_IF1_OD | Open-drain NOR gate with two inputs and enable input. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | PCH_IF0 | Simple PMOS transistor for precharging. |
| ALU_AND0-ALU_AND7 | AND2_ALU | AND gate with two inputs. |
| ALU_CGGEN_H?,ALU_CGGEN_L? | ALU_CGEN | Logic for generating carry signals for the CLA (carry lookahead adder). |
| ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER?,ALU_DECODER? | ALU_DECODER | AND gate with two inputs. |
| ALU_DFF? | DFFN_EE_Q_ALU_SIGN | Semi-dynamic data flip-flop with externally inverted enable inputs, level-sensitive D-gating, and no inverted output. |
| ALU_NOT1-ALU_NOT8,ALU_NOT10 | NOT_PCH_X2_ALU | Inverter with precharge. Precharge has 2× drive strength. |
| ALU_NOT9 | NOT_PCH_X1_ALU | Inverter with precharge. |
| ALU_NOT11 | NOT_ALU_A | Simple inverter. |
| ALU_NOT12 | NOT_ALU_B | Simple inverter. |
| ALU_PGGEN0-ALU_PGGEN7 | ALU_PGGEN | Logic for generating P/G (propagate/generate) signals for the CLA (carry lookahead adder). |
| ALU_RESULT0-ALU_RESULT7 | AO221_XOR_IN4_S1 | 2-2-1 AND-OR two-level compound gate with XOR gate feeding IN4, and shared IN1 between both gates. The XOR gate in this cell functions as the sum generator of the carry lookahead adder (CLA). |
| ALU_SHIFTER?,ALU_SHIFTER?,ALU_SHIFTER?,ALU_SHIFTER?,ALU_SHIFTER?,ALU_SHIFTER?,ALU_SHIFTER?,ALU_SHIFTER? | ALU_SHIFTER | Logic for shifting and rotating 8 bit data word. |
| ALU_ZGEN? | NOR8_ALU | NOR gate with eight inputs. |
| DBUS_BRIDGE0-DBUS_BRIDGE7 | B2B_WAND_INJ_A | Bidirectional bus bridge with wired-AND behavior (open-drain), active-low output enable, active-low precharge, and open-drain injector on side A. |
| DBUS_NAND0,DBUS_NAND2,DBUS_NAND4,DBUS_NAND6 | NAND2_OD_A_DBUS | Open-drain NAND gate with two inputs. |
| DBUS_NAND1,DBUS_NAND3,DBUS_NAND5,DBUS_NAND7 | NAND2_OD_B_DBUS | Open-drain NAND gate with two inputs. |
| DBUS_NOT0-DBUS_NOT7 | NOT_DBUS | Simple inverter. |
| DEC1_NOT1-DEC1_NOT24,DEC1_NOT26-DEC1_NOT53 | NOT2_PCH_DEC1 | Two inverters with precharge. |
| DEC1_NOT56-DEC1_NOT65,DEC1_NOT67,DEC1_NOT69,DEC1_NOT71 | NOT_DEC1 | Simple inverter. |
| DEC2_NOT1-DEC2_NOT5,DEC2_NOT9-DEC2_NOT16,DEC2_NOT19,DEC2_NOT20,DEC2_NOT22-DEC2_NOT31 | NOT_X1_DEC2 | Simple inverter. |
| DEC2_NOT7,DEC2_NOT8,DEC2_NOT17,DEC2_NOT18 | NOT_X1_P2_DEC2 | Inverter with 2× PMOS drive strength. |
| DEC2_NOT21 | NOT_X1_PCH_DEC2 | Inverter with precharge. |
| DEC2_PCH1 | PCH_DEC2_A | Simple PMOS transistor for precharging. |
| DEC2_PCH2,DEC2_PCH3 | PCH_DEC2_C | Simple PMOS transistor for precharging. |
| DEC2_PCH4 | PCH_DEC2_B | Simple PMOS transistor for precharging. |
| DEC3_NOR1,DEC3_NOR2 | NOR2_PCH_IN1_DEC3 | NOR gate with two inputs and precharge on input 1. |
| DEC3_NOT1-DEC3_NOT15,DEC3_NOT17-DEC3_NOT22,DEC3_NOT25,DEC3_NOT32,DEC3_NOT33,DEC3_NOT42-DEC3_NOT46,DEC3_NOT53,DEC3_NOT58-DEC3_NOT67 | NOT_PCH_DEC3_A | Inverter with precharge. |
| DEC3_NOT16,DEC3_NOT30,DEC3_NOT49-DEC3_NOT52,DEC3_NOT56 | NOT_PCH_DEC3_B | Inverter with precharge. |
| DEC3_NOT23,DEC3_NOT26-DEC3_NOT28,DEC3_NOT34-DEC3_NOT36,DEC3_NOT47,DEC3_NOT48,DEC3_NOT54,DEC3_NOT55,DEC3_NOT57 | NOT_P2_PCH_DEC3 | Inverter with 2× PMOS drive strength, and precharge. |
| DEC3_NOT24,DEC3_NOT31,DEC3_NOT37 | NOT_PCH_DEC3_A2 | Inverter with precharge. |
| DEC3_NOT29,DEC3_NOT38-DEC3_NOT41 | NOT_PCH_DEC3_B2 | Inverter with precharge. |
| DEC3_NOT69,DEC3_NOT70,DEC3_NOT73,DEC3_NOT74 | NOT_P2_DEC3_A | Inverter with 2× PMOS drive strength. |
| DEC3_NOT71,DEC3_NOT72 | NOT_P2_DEC3_B | Inverter with 2× PMOS drive strength. |
| FLAG_C?,FLAG_H?,FLAG_N?,FLAG_Z? | DFFN_EE_PCH_D_ALU_FLAG | Semi-dynamic data flip-flop with externally inverted enable inputs, level-sensitive D-gating, and prechargable D input. |
| IDU0 | IDU_BIT0 | Bits 0 and 8 of the 16 bit increment/decrement unit. |
| IDU1-IDU6 | IDU_BIT123456 | Bits 1-6 and 9-14 of the 16 bit increment/decrement unit. |
| IDU7 | IDU_BIT7 | Bits 7 and 15 of the 16 bit increment/decrement unit. |
| IDU_CTL? | IDU_CTL | Logic for increment/decrement unit. |
| IDU_MUX_H0-IDU_MUX_H6 | MUX_IDU_H | Multiplexer with two inputs. |
| IDU_MUX_L0-IDU_MUX_L7 | MUX_IDU_L | Multiplexer with two inputs. |
| IDU_NOT0-IDU_NOT7 | NOT2_IDU | Two simple inverters. |
| IDU_XOR_H0-IDU_XOR_H7 | XOR_IDU_H | XOR gate with two inputs. |
| IDU_XOR_L0-IDU_XOR_L7 | XOR_IDU_L | XOR gate with two inputs. |
| IRQ_AND? | AND2_IRQ | AND gate with two inputs. |
| IRQ_HEAD?,IRQ_HEAD?,IRQ_HEAD?,IRQ_HEAD?,IRQ_HEAD? | NOT5_IRQ | Five simple inverters. |
| IRQ_LATCH0-IRQ_LATCH7 | DLATCH_EE_IRQ | Gated data latch with externally inverted enable inputs and additional dynamically controlled inverted output. |
| IRQ_NAND2_NAND3_0-IRQ_NAND2_NAND3_7 | NAND2_NAND3_OD_IRQ | NAND gate with two inputs and open-drain NAND gate with three inputs. |
| IRQ_PRIO0 | IRQ_PRIO_BIT0 | Interrupt priority decoding and other interrupt related logic. |
| IRQ_PRIO1 | IRQ_PRIO_BIT1 | Interrupt priority decoding and other interrupt related logic. |
| IRQ_PRIO2 | IRQ_PRIO_BIT2 | Interrupt priority decoding and other interrupt related logic. |
| IRQ_PRIO3 | IRQ_PRIO_BIT3 | Interrupt priority decoding and other interrupt related logic. |
| IRQ_PRIO4 | IRQ_PRIO_BIT4 | Interrupt priority decoding and other interrupt related logic. |
| IRQ_PRIO5 | IRQ_PRIO_BIT5 | Interrupt priority decoding and other interrupt related logic. |
| IRQ_PRIO6 | IRQ_PRIO_BIT6 | Interrupt priority decoding and other interrupt related logic. |
| IRQ_PRIO7 | IRQ_PRIO_BIT7 | Interrupt priority decoding and other interrupt related logic. |
| REG_A0-REG_A7,REG_IR0-REG_IR7 | DFF_CC_EE_Q_X2_REG_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, 2× drive strength, and no inverted output. |
| REG_AND2_AND3 | AND2_AND3_REG | Group of two AND gates with two and three inputs. |
| REG_AND? | AND2_REG | AND gate with two inputs. |
| REG_A_NOT_WE? | NOT_REG_A_WE | Simple inverter. |
| REG_A_OUT0-REG_A_OUT7 | REG_A_OUT | Output drivers for A registers. |
| REG_B0-REG_B7,REG_C0-REG_C7,REG_D0-REG_D7,REG_E0-REG_E7,REG_H0-REG_H7,REG_L0-REG_L7 | DFF_CC_EE_Q_X1_REG_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, and no inverted output. |
| REG_BC_OUT0-REG_BC_OUT7 | REG_BC_OUT | Output drivers for BC registers. |
| REG_BUS_PCH_A0-REG_BUS_PCH_A3 | REG_BUS_PCH_A_BIT0123 | Precharger and zero output for register busses bits 0-3. |
| REG_BUS_PCH_A4 | REG_BUS_PCH_A_BIT4 | Precharger and zero output for register busses bit 4. |
| REG_BUS_PCH_A5 | REG_BUS_PCH_A_BIT5 | Precharger and zero output for register busses bit 5. |
| REG_BUS_PCH_A6 | REG_BUS_PCH_A_BIT6 | Precharger and zero output for register busses bit 6. |
| REG_BUS_PCH_A7 | REG_BUS_PCH_A_BIT7 | Precharger and zero output for register busses bit 7. |
| REG_BUS_PCH_B0-REG_BUS_PCH_B7 | REG_BUS_PCH_B | Precharger for register busses. |
| REG_B_NOT_WE? | NOT_REG_B_WE | Simple inverter. |
| REG_C_NOT_WE?,REG_D_NOT_WE?,REG_IR_NOT_WE?,REG_W_NOT_WE?,REG_Z_NOT_WE? | NOT_REG_WE | Simple inverter. |
| REG_DE_OUT0-REG_DE_OUT7 | REG_DE_OUT | Output drivers for DE registers. |
| REG_E_NOT_WE?,REG_H_NOT_WE? | NOT_REG_H_E_WE | Simple inverter. |
| REG_HL_OUT0-REG_HL_OUT7 | REG_HL_OUT | Output drivers for HL registers. |
| REG_IE0-REG_IE7 | DFFR_CC_EE_REG_IE_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, and active-high reset gated by the clock level. |
| REG_IE_NOT_WE? | NOT_REG_IE_WE | Simple inverter. |
| REG_L_NOT_WE? | NOT_REG_L_WE | Simple inverter. |
| REG_NOT0-REG_NOT7 | NOT_REG | Simple inverter. |
| REG_OA1,REG_OA2 | OA21_REG | 2-1 OR-AND two-level compound gate. |
| REG_OR? | OR2_TAP_NOR_TAP_IN1_N_REG | OR gate with two inputs, tap on intermediate NOR, and inverting tap on IN1. |
| REG_PCH0-REG_PCH7,REG_PCL0-REG_PCL7 | DFFS_CC_EE_PCH_D_REG_PC_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, prechargable D input, and active-low set gated by the clock level. |
| REG_PCH_NOT_WE?,REG_PCH_NOT_WE?,REG_PCL_NOT_WE?,REG_PCL_NOT_WE? | NOT2_REG_PC_WE | Two simple inverters. |
| REG_PC_OUT0-REG_PC_OUT2 | REG_PC_OUT_BIT012 | Output drivers for PC register bits 0-2. |
| REG_PC_OUT3-REG_PC_OUT5 | REG_PC_OUT_BIT345 | Output drivers for PC register bits 3-5. |
| REG_PC_OUT6,REG_PC_OUT7 | REG_PC_OUT_BIT67 | Output drivers for PC register bits 6 and 7. |
| REG_SPH0-REG_SPH7,REG_SPL0-REG_SPL7 | DFF_CC_EE_PCH_D_REG_SP_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, and prechargable D input. |
| REG_SPH_NOT_WE?,REG_SPL_NOT_WE? | NOT_REG_SP_WE | Simple inverter. |
| REG_SP_OUT0-REG_SP_OUT7 | REG_SP_OUT | Output drivers for SP registers. |
| REG_W0-REG_W7,REG_Z0-REG_Z7 | DFF_CC_EE_Q_N_REG_WZ_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, and no non-inverted output. |
| REG_WZ_OUT0-REG_WZ_OUT7 | REG_WZ_OUT | Output drivers for WZ registers. |
| VEQU? | AND2_IN1_N_TAP_IN1 | AND gate with two inputs, inverted first input, and tap after inversion of first input. |
| WAFR? | NOR2_E | NOR gate with two inputs. |
| WAGR? | NOR2_D | NOR gate with two inputs. |
| WDIN? | OA21 | 2-1 OR-AND two-level compound gate. |
| WEEN? | NAND2_IN1_N_B | NAND gate with two inputs, one of them inverted. |
| WERF? | NAND2_IN1_N_A | NAND gate with two inputs, one of them inverted. |
| WUDZ? | NAND2_IN1_N_C | NAND gate with two inputs, one of them inverted. |
| XAYM?,XDQF?,XIRF?,YDXA?,YOII?,YSBT?,ZACW?,ZAZA?,ZIVV?,ZKAI?,ZKDU?,ZORP?,ZRBY? | DFF_CC_Q | Single-edge-triggered data flip-flop with complementary clock inputs and no inverted output. |
| XOGS? | AO31_IN3_N | 3-1 AND-OR two-level compound gate with inverted third input. |
| XTIP? | AOI21_B | 2-1 AND-OR-INVERT two-level compound gate. |
| XUDO? | NOT_F | Simple inverter. |
| XUFU? | DFF_CC_Q_ALT | Single-edge-triggered data flip-flop with complementary clock inputs and no inverted output. |
| XURG? | DFFRE_CC_Q | Semi-dynamic data flip-flop with complementary clock inputs, level-sensitive D-gating, active-high reset gated by the clock level, and no inverted output. |
| XURI? | NOT_D | Simple inverter. |
| XWEE? | NOT_E | Simple inverter. |
| XYGB? | NOR3 | NOR gate with three inputs. |
| YCNF? | OR3_B | OR gate with three inputs. |
| YEPJ? | NOT_C | Simple inverter. |
| YKUA? | OAI21 | 2-1 OR-AND-INVERT two-level compound gate. |
| YNEU? | AOI21_A | 2-1 AND-OR-INVERT two-level compound gate. |
| YNIU? | NOR2_C | NOR gate with two inputs. |
| YNKW? | SRLATCH_R_N_ALT | SR-latch with active-high set input and active-low reset input. Reset takes precedence when both inputs are asserted. |
| YNOZ? | OR3_A | OR gate with three inputs. |
| YODP? | DLATCH_EE_Q_N | Gated data latch with externally inverted enable inputs and no non-inverted output. |
| YOLU? | NOR2_IN2_N | NOR gate with two inputs, one of them inverted. |
| ZAIJ? | NOR4_IN2_N_IN4_N | NOR gate with four inputs, two of them inverted. |
| ZAOC? | NAND2_C | NAND gate with two inputs. |
| ZBPP? | AO33_S3_TAP_IN1_N | 3-3 AND-OR two-level compound gate with shared IN3, and inverting tap on IN1. |
| ZFEX? | OR2_B | OR gate with two inputs. |
| ZGNA? | NOT_A | Simple inverter. |
| ZHZO? | NOR2_F | NOR gate with two inputs. |
| ZIKS? | NAND2_D | NAND gate with two inputs. |
| ZJBF? | NOT_X3_P2 | Inverter with 3× drive strength and a PMOS-to-NMOS size ratio of 2:1. |
| ZJJE?,ZKOG?,ZLOZ?,ZOJZ?,ZRSY?,ZUMN? | SRLATCH_R_N | SR-latch with active-high set input and active-low reset input. Reset takes precedence when both inputs are asserted. |
| ZKON? | NOT_G | Simple inverter. |
| ZLYZ? | OA211_IN1_N_IN3_N | 2-1-1 OR-AND two-level compound gate with inverted IN1 and IN3. |
| ZNDA? | OR2_A | OR gate with two inputs. |
| ZOWA? | NOR2_A | NOR gate with two inputs. |
| ZOXC? | NAND2_A | NAND gate with two inputs. |
| ZUDN? | NOT_B | Simple inverter. |
| ZWLM? | NOR2_B | NOR gate with two inputs. |
| ZWUU? | AOI331_S3 | 3-3-1 AND-OR-INVERT two-level compound gate with shared IN3. |
| ZZOM? | NAND2_B | NAND gate with two inputs. |